Flux-1 RSFQ microprocessor: physical design and test results

Author

Bunyk, Paul ; Leung, Mike ; Spargo, John ; Dorojevets, Mikhail

Author_Institution

Space & Electron., TRW Inc., Redondo Beach, CA, USA

Volume

13

Issue

2

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

433

Lastpage

436

Abstract

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60 K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification.

Keywords

circuit CAD; circuit layout CAD; formal verification; high level synthesis; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit layout; microprocessor chips; superconducting processor circuits; 20 GHz; CAD tools; Flux-1 RSFQ microprocessor; Josephson junctions; RSFQ design methodology; chip physical design; design automation; design verification; gate interconnect; general-purpose processing engine; passive transmission lines; Circuit synthesis; Clocks; Design automation; Design methodology; Digital systems; Engines; Frequency; Josephson junctions; Microprocessors; Testing;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2003.813890

Filename

1211634