Title :
Architectural and implementation challenges in designing high-performance RSFQ processors: a FLUX-1 microprocessor and beyond
Author :
Dorojevets, Mikhail ; Bunyk, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA
fDate :
6/1/2003 12:00:00 AM
Abstract :
This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW´s 4 kA/cm2, 1.75-μm Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm ×10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.
Keywords :
flip-chip devices; high-speed integrated circuits; microprocessor chips; parallel architectures; pipeline processing; superconducting processor circuits; 1.75 micron; 10.35 mm; 10.65 mm; 20 GHz; 8 bit; FLUX-1 RSFQ microprocessor; FLUX-1R; Josephson junction technology; RSFQ logic; flip-chip packaging; high-performance RSFQ processor design; microprocessor design; parallel partitioned architecture; petaflops computing; processing pipelines; superconductor processor architecture; Clocks; Collaboration; Frequency; Integrated circuit interconnections; Josephson junctions; Microprocessors; NASA; Pipelines; Process design; Space technology;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2003.813893
