Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 ??m ?? 55 ??m, uses decoupling capacitance to sense noise and inject a proportional current into V_SS as a method of reduction. A chip has been designed and fabricated using TSMC´s 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.