• DocumentCode
    1237036
  • Title

    Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays

  • Author

    Hsu, Chun-Lung ; Cheng, Chang-Hsin ; Liu, Yu

  • Author_Institution
    Dept. of Electr. Eng., Nat. Dong HwaUniversity, Shou-Feng, Taiwan
  • Volume
    18
  • Issue
    2
  • fYear
    2010
  • Firstpage
    319
  • Lastpage
    324
  • Abstract
    This paper develops a built-in self-detection/correction (BISDC) architecture for motion estimation computing arrays (MECAs). Based on the error detection/correction concepts of biresidue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in self-correction circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area overhead and timing penalty.
  • Keywords
    error correction; error detection; logic arrays; motion estimation; residue codes; video coding; biresidue codes; built-in self-correction circuits; built-in self-detection architecture; error correction; error detection; minor area overhead; motion estimation computing arrays; timing penalty; Area overhead; built-in self-correction (BISC); built-in self-detection (BISD); motion estimation computing array (MECA);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2008.2009452
  • Filename
    4814472