In-System Silicon Validation and Debug

Silicon validation - proving a chip works correctly at speed and in system under different operating conditions - is always necessary, even for a "perfect" design. Silicon debug - finding the root cause of a malfunction - is necessary whenever a design is not flawless. First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip\´s development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. The difficulty of silicon validation will increase at 65 nm and below because existing ad hoc methodologies don\´t scale with the unprecedented levels of SoC device complexity. Even the most sophisticated SoC design methodology cannot fully account for all the parameters that affect silicon behavior, or for all logic corner cases occurring in the life of a chip working at speed and in system. For example, the simultaneous occurrence of two unlikely events might not be anticipated pre- silicon, so it is never simulated or analyzed; however, when it occurs in system, it can cause unexpected behavior. Presilicon verification methods - simulation, emulation, FPGA prototyping, timing analysis, and formal verification - don\´t address many deep-submicron problems that occur in the actual device.