DocumentCode
1237763
Title
Case Study on Speed Failure Causes in a Microprocessor
Author
Killpack, Kip ; Natarajan, Suriyaprakash ; Krishnamachary, Arun ; Bastani, Pouria
Author_Institution
Intel Corp., Hillsboro, OR
Volume
25
Issue
3
fYear
2008
Firstpage
224
Lastpage
230
Abstract
In this article, we identify the underlying speed paths and perform a detailed analysis on the effects of multiple input switching, cross-coupling noise, and localized voltage drop on microprocessor. We employ cycle-wise clock shrinks on a tester combined with a CAD methodology to unintrusively identify and analyze these speed paths. Understanding the causes of speed failures can help designers make better power and performance tradeoffs.
Keywords
logic CAD; logic testing; microprocessor chips; cross-coupling noise; cycle-wise clock; localized voltage drop; logic CAD; logic testing; microprocessor; multiple input switching; speed failure; Clocks; Design automation; Failure analysis; Frequency; Microprocessors; Performance analysis; Silicon; Testing; Time to market; Voltage; critical path; cross-coupling noise; diagnosis; marginality; microprocessor; multiple-input switching; silicon debug; voltage droop;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2008.61
Filename
4534161
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