Linking Statistical Learning to Diagnosis

As device and interconnect feature sizes shrink, silicon chip behavior becomes more sensitive to process and environmental variations and uncertainties. During the design phase, many effects of these variations are not explicitly or accurately modeled and simulated, either because doing so is too expensive or because the designer is not aware that a particular effect can significantly alter chip timing. When a significant timing-behavior mismatch occurs between design and silicon, it would be useful to identify the unmodeled effects that contribute most to the mismatch. Traditional diagnosis of defects is based on an assumed fault model. A failing chip is diagnosed to find the subset of faults that can best explain the failure. In this article, we propose a new type of diagnosis that explains mismatches between predicted and observed timing behavior. We assume that design-silicon timing mismatch is due to unmodeled systematic and random timing effects. Our goal is to uncover the most important systematic effects. To observe a mismatch, we measure the delays of a set of critical paths on a collection of sample chips. We compare the measured and the predicted path delays. Their differences reflect the timing mismatch. We do not discuss the measurement method in detail here, but rather we focus on the diagnosis algorithm.