DocumentCode :
1237800
Title :
Physical Techniques for Chip-Backside IC Debug in Nanotechnologies
Author :
Boit, Christian ; Schlangen, Rudolf ; Kerst, Uwe ; Lundquist, Ted
Author_Institution :
Berlin Univ. of Technol., Berlin
Volume :
25
Issue :
3
fYear :
2008
Firstpage :
250
Lastpage :
257
Abstract :
Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going.
Keywords :
failure analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; nanoelectronics; chip-backside IC debugging; final defect confirmation; flip-chip packaging; metal layers; nanotechnologies; physical failure analysis; semiconductor technology; Circuits; Failure analysis; Functional analysis; Laser theory; Milling; Nanoscale devices; Particle beams; Photonic band gap; Silicon on insulator technology; Voltage; backside; debug; electron beam probing; laser voltage probing; nanoscale; optical probing; photoelectric laser stimulation; thermal laser stimulation; time-resolved emission;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2008.82
Filename :
4534166
Link To Document :
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