• DocumentCode
    1238092
  • Title

    Tracking down the chip killers [IC design verification]

  • Author

    Edwards, Chris

  • Volume
    50
  • Issue
    12
  • fYear
    2004
  • Firstpage
    44
  • Lastpage
    46
  • Abstract
    As integration levels soar, formal methods are playing an increasing role in helping to crack the chip verification conundrum. This article considers the process of IC design, verification, simulation and test, with emphasis on formal verification and assertion methods.
  • Keywords
    circuit simulation; formal verification; integrated circuit design; integrated circuit modelling; integrated circuit testing; IC design verification; IC simulation; IC test; assertion methods; formal methods; formal verification;
  • fLanguage
    English
  • Journal_Title
    IEE Review
  • Publisher
    iet
  • ISSN
    0953-5683
  • Type

    jour

  • DOI
    10.1049/ir:20041206
  • Filename
    1395335
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1238092