DocumentCode
1238760
Title
CMOS analogue adder
Author
Chaoui, Hicham
Author_Institution
CEMIP, Paris VII Univ.
Volume
31
Issue
3
fYear
1995
fDate
2/2/1995 12:00:00 AM
Firstpage
180
Lastpage
181
Abstract
A CMOS analogue circuit is proposed that computes the sum of two voltages. The circuit is self-biased, only requires a small number of transistors, and offers good accuracy over a wide range of input values. The design makes no special demands on device aspect ratios and could offer an economic alternative to conventional approaches. Simulation results have shown that total harmonic distortion (THD) is lower than -40 dB for output voltages up to 4 V peak to peak
Keywords
CMOS analogue integrated circuits; adders; analogue computer circuits; analogue processing circuits; harmonic distortion; 4 V; CMOS analogue adder; THD; self-biased circuit; total harmonic distortion;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19950136
Filename
362576
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