DocumentCode :
123909
Title :
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy
Author :
Kumar Rethinagiri, Santhosh ; Palomar, Oscar ; Sobe, Anita ; Knauth, Thomas ; Barczynski, Wojciech ; Yalcin, Gulay ; Hayduk, Yarco ; Cristal, Adrian ; Unsal, Ozan ; Felber, Pascal ; Fetzer, Christof ; Ryckaert, J. ; Alioto, Gina
Author_Institution :
Barcelona Supercomput. Center-Centro Nac. de Supercomputacion (BSC), Barcelona, Spain
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
191
Lastpage :
198
Abstract :
Dramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On one hand, designers use technology scaling as one of the methods to face the phenomenon called dark silicon (only segments of a chip function concurrently due to power restrictions). On the other hand, designers use extreme-scale systems such as teradevices to meet the performance needs of their applications which in turn increases the power consumption of the platform. In order to overcome these challenges, we need novel computing paradigms that address energy efficiency. One of the promising solutions is to incorporate parallel distributed methodologies at different abstraction levels. The FP7 project ParaDIME focuses on this objective to provide different distributed methodologies (software-hardware techniques) at different abstraction levels to attack the power-wall problem. In particular, the ParaDIME framework will utilize: circuit and architecture operation below safe voltage limits for drastic energy savings, specialized energy-aware computing accelerators, heterogeneous computing, energy-aware runtime, approximate computing and power-aware message passing. The major outcome of the project will be a processor architecture for a heterogeneous distributed system that utilizes future device characteristics for drastic energy savings. Wherever possible, ParaDIME will adopt multidisciplinary techniques, such as hardware support for message passing, runtime energy optimization utilizing new hardware energy performance counters, use of accelerators for error recovery from sub-safe voltage operation, and approximate computing through annotated code. Furthermore, we will establish and investigate the theoretical limits of energy savings at the device, circuit, architecture, runtime and programming model levels of the computing stack, as well as quantify the actual energy savings achieved by the Par- DIME approach for the complete computing stack with the real environment.
Keywords :
computer centres; energy conservation; energy consumption; message passing; parallel architectures; power aware computing; FP7 project; ParaDIME; approximate computing; computing devices; dark silicon; data centers; drastic energy savings; energy consumption; energy efficiency; energy minimization; energy optimization; energy-aware computing accelerators; energy-aware runtime; heterogeneous computing; heterogeneous distributed system; parallel distributed infrastructure; parallel distributed methodologies; power consumption; power-aware message passing; teradevices; voltage limits; Computer architecture; Energy consumption; Hardware; Message passing; Performance evaluation; Runtime; Servers; Data center; Energy minimization; Heterogeneous devices; Low-power; Programming model;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2014 17th Euromicro Conference on
Conference_Location :
Verona
Type :
conf
DOI :
10.1109/DSD.2014.27
Filename :
6927244
Link To Document :
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