DocumentCode :
123925
Title :
Fault Tolerant Duplex System with High Availability for Practical Applications
Author :
Vit, Pavel ; Borecky, Jaroslav ; Kohlik, Martin ; Kubatova, Hana
Author_Institution :
Dept. of Digital Design, Czech Tech. Univ., Prague, Czech Republic
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
320
Lastpage :
325
Abstract :
This paper presents the method of dependability parameters improvement for systems based on unreliable components such as Field Programmable Gate Arrays (FPGAs). It combines Concurrent Error Detection (CED) techniques [4], FPGA dynamic reconfigurations and our previously designed Modified Duplex System (MDS) architecture. The methodology is developed with respect to the minimal area overhead and high availability. It is aimed for mission critical practical applications of modular systems. Therefore it is applied and tested on the safety railway station system, where all these parameters are required. This Fault-Tolerant (FT) design is modeled and tested to fulfill strict Czech standards [7]. The proposed method is based on static and partial dynamic reconfiguration [5] of totally self-checking blocks which allows a full recovery from a Single Even Upset (SEU). This method is compared with triple module redundancy technique.
Keywords :
error detection; fault tolerance; field programmable gate arrays; integrated circuit design; logic testing; radiation hardening (electronics); safety systems; CED techniques; Czech standards; FPGA dynamic reconfigurations; FT design; MDS architecture; SEU; concurrent error detection techniques; dependability parameter improvement; fault tolerant duplex system; fault-tolerant design; field programmable gate arrays; modified duplex system architecture; modular systems; module redundancy technique; partial dynamic reconfiguration; safety railway station system; self-checking blocks; single event upset; static reconfiguration; Availability; Distribution functions; Field programmable gate arrays; Maintenance engineering; Safety; Tunneling magnetoresistance; Wires; FPGA; SEU; TMR; availability; dependability; duplex system; reconfiguration; reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2014 17th Euromicro Conference on
Conference_Location :
Verona
Type :
conf
DOI :
10.1109/DSD.2014.54
Filename :
6927260
Link To Document :
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