Improving Power of Cache and Register File through Critical Path Instructions

As feature size shrinks, power becomes one of the limiting factors in design of modern processors. Cache and register-file are the two power hungry components in processors, consuming more than one third of total processors´ power budget. In this work, we propose a new architecture for cache and register-file which exploits critical path instructions to reduce power consumption. In this architecture, we have cache and register-file cells operating at two different voltage levels and we change the structure of the cells so that they dynamically switch between nominal and reduced supply voltages. Those cells that are accessed frequently by critical instructions are assigned to use nominal supply voltage to preserve performance. On the other side, the cells that are rarely accessed by critical instructions are assigned to low supply voltage to reduce power consumption. To reduce performance impact of voltage switching, we monitor critical instructions within long intervals and adjust the voltage of cells only when the intervals are elapsed. Our simulation results reveal that our optimization technique results in significant power saving with negligible effect on performance.