Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops

The estimation of dependable noise margins in digital cells is increasingly significant as nano-scale CMOS technology is facing true reliability issues. On one hand, a major concern comes from circuit aging mechanisms, such as NBTI, which degrade the reliability of circuit operation over time. On the other hand, variability in technology parameters results in affecting reliability. The impact of such phenomena is particularly related to the noise margins in the memory elements of a design, since a wrong stored logic value results in an upset of the system state. This work quantifies and compares the joint effect of process variations and of NBTI aging over the years on the real noise margins of several flip-flop cells. The huge amount of transistor level Monte Carlo simulations produced both nominal (i.e. average) values and associated standard deviations of the noise margins of the selected flip-flops. A possible concept of utilization of the acquired noise margin data is also reported.