Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks

Execution of cryptographic algorithm in hardware or software usually leaves power/current traces that are dependent on the data being processed. Power analysis attacks (PAAs) have been found to be extremely effective on such systems to derive the cryptographic secrets from these traces. Therefore, countering PAAs is of great importance. In this work, a Binary Decision Diagram (BDD) based dual-rail logic circuit scheme has been developed to counter PAAs. This circuit scheme features novel pre-charge generation, voltage scaling with leakage power minimization and early propagation effect resistance mechanism. A simple synthesis algorithm for mapping given Boolean functions to such BDD based circuits is also presented. The synthesized circuits feature low power circuitry and extremely low peak power variation. Experimental results for elementary gates such as AND, OR, NOT, XOR, NAND, NOR and the Lucifer and the Present S-boxes highlight the advantages of circuits based on this scheme with respect to peak power variance, average power and average current when compared with two other techniques - DP-BDD and SDMLp. Resistance of our S-box implementations to strong differential power analysis and correlation power analysis attacks have also been experimentally demonstrated. All results have been obtained using 65nm technology.