DocumentCode :
1239628
Title :
Linear models for keystream generators
Author :
Golic, Jovan Dj
Author_Institution :
Inf. Security Res. Centre, Queensland Univ. of Technol., Brisbane, Qld., Australia
Volume :
45
Issue :
1
fYear :
1996
fDate :
1/1/1996 12:00:00 AM
Firstpage :
41
Lastpage :
49
Abstract :
It is shown that an arbitrary binary keystream generator with M bits of memory can be linearly modeled as a non-autonomous linear feedback shift register of length at most M with an additive input sequence of nonbalanced identically distributed binary random variables. The sum of the squares of input correlation coefficients over all the linear models of any given length proves to be dependent on a keystream generator. The minimum and maximum values of the correlation sum along with the necessary and sufficient conditions for them to be achieved are established. An effective method for the linear model determination based on the linear sequential circuit approximation of autonomous finite-state machines is developed. Linear models for clock controlled shift registers and arbitrary shift register based keystream generators are derived. Several examples including the basic summation generator, the clock-controlled cascade, and the shrinking generator are presented. Linear models are the basis for a general structure-dependent and initial-state-independent statistical test. They may also be used for divide and conquer correlation attacks on the initial state. Security against the corresponding statistical attack appears hard to control in practice and generally hard to achieve with simple keystream generator schemes
Keywords :
cryptography; finite state machines; shift registers; binary random variables; clock-controlled shift registers; correlation coefficients; cryptography; divide and conquer correlation attacks; finite-state machines; keystream generators; linear feedback shift register; linear models; shift register; Circuit testing; Clocks; Linear approximation; Linear feedback shift registers; Random variables; Security; Sequential analysis; Sequential circuits; Shift registers; Sufficient conditions;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.481485
Filename :
481485
Link To Document :
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