DocumentCode :
123977
Title :
PBO-Based Test Compression
Author :
Balcarek, Jiri ; Fier, Petr ; Schmidt, J.
Author_Institution :
Dept. of Digital Design, Czech Tech. Univ. in Prague, Prague, Czech Republic
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
679
Lastpage :
682
Abstract :
This paper presents a novel ATPG and test compression algorithm based on Pseudo-Boolean (PBO) optimization. Similarly to SAT-based ATPGs, the test for each fault is represented implicitly as a PBO instance. The optimization process solves the problem of maximizing the number of unspecified values in the test. A novel don´t care aware circuit-to-PBO conversion procedure is presented. The obtained unspecified values in the test are efficiently exploited in test compression. The produced compressed test sequence is suited for the RESPIN decompression architecture, thus for testing systems on-chip. The presented experimental results show the efficiency and competitiveness of the proposed method.
Keywords :
Boolean algebra; automatic test pattern generation; logic testing; system-on-chip; ATPG; PBO-based test compression; RESPIN decompression architecture; SAT; circuit-to-PBO conversion; pseudo-Boolean optimization; systems on-chip; test compression algorithm; Automatic test pattern generation; Benchmark testing; Circuit faults; Logic gates; Optimization; Vectors; ATPG; Pseudo-Boolean Optimization; RESPIN; SoC testing; test compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2014 17th Euromicro Conference on
Conference_Location :
Verona
Type :
conf
DOI :
10.1109/DSD.2014.86
Filename :
6927312
Link To Document :
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