Design and Implementation of an Efficient Fingerprint Features Extractor

Biometric recognition systems are rapidly evolving technologies and their use in embedded devices for accessing and managing data and resources is a very challenging issue. Usually, they are composed of three main modules: Acquisition, Features Extraction and Matching. In this paper the hardware design and implementation of an efficient fingerprint features extractor for embedded devices is described. The proposed architecture, designed for different acquisition sensors, is composed of four blocks: Image Pre-processor, Macro-Features Extractor, Micro- Features Extractor and Master Controller. The Image Pre- processor block increases the quality level of the input raw image and performs an adaptive binarization, introducing a novel hardware approach. The Macro-Features Extractor extracts singularity points. The Micro-Features Extractor extracts only micro-features around singularity points using an adaptive thinning and a post-processing phase to remove potential false micro-features. The Master Controller synchronizes and coordinates the two extractors. Xilinx ML507 board has been used to develop the prototype, while tests have been conducted on the PolyU (Hong Kong Polytechnic University) and the FVC2002 DB2-B free databases. These two databases have been chosen for their different characteristics in terms of image resolution and dimension in order to test the effectiveness of the proposed architecture. Experimental results show an interesting trade-off between used resources (about 32%) and fingerprint features extraction time (the lower execution time is 21.6 ms while the higher execution time is 28.4 ms, with a working frequency of 25 MHz), obtaining the best rate of false minutiae discharged of 5%.