Generation of minimal vertex covers for row/column allocation in self-repairable arrays

Author

Smith, Michael D. ; Mazumder, Pinaki

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

Issue

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

109

Lastpage

115

Abstract

This paper lays foundations for an approach to on-chip row/column allocation that exploits certain properties offered by laterally connected networks of simple threshold devices. As a sample application, it is demonstrated how electronic implementations of these networks can be used as the basis for effective memory array repair systems that require little hardware overhead

Keywords

fault tolerant computing; graph theory; logic arrays; redundancy; embedded memory; memory array repair systems; minimal vertex covers; neural network; redundant memory; row/column allocation; self-repairable arrays; threshold devices; Algorithm design and analysis; Circuit faults; Fabrication; Integrated circuit manufacture; Intelligent networks; Manufacturing automation; Network-on-a-chip; Neural network hardware; Neural networks; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.481492

Filename

481492

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1239914