Using high-level knowledge to enhance data channels in FPGA streaming systems

FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming to be prohibitive. This necessitates using high-level programming tools to transparently handle low-level aspects - thus simplifying the design process. Examples of high-level tools for building streaming systems include MaxCompiler by Maxeler Technologies and DSP Builder by Altera. We propose an interception layer which when inserted into communication channels, transparently enhances their performance and capabilities without needing to modify the streaming kernels or host code. We discuss specific channel enhancements: lossless compression to improve effective bandwidth; error correction and fault tolerance to improve reliability. The interception layer is intended to add complex behaviour while maintaining the simplicity of the high-level abstraction when transmitting data via a channel.