Fast simulation of HDL models

Using large application specific integrated circuits (ASICs), typically with at least 50,000 (50K) gates, is on the rise. Hardware design methodology has turned to CAE (computer-aided engineering) tools to simulate and verify performance. These tools are usually called hardware description languages (HDLs). Digital systems are becoming increasingly complex. Simulating designs using conventional or optimized (sequential) HDL simulators, or even specialized hardware accelerators, cannot keep up with this growth. It is not unusual for a single simulation run with one test vector for a 50K ASIC design to take hours. This definitely increases the hardware design cost and prolongs the time-to-market. One solution to this time problem is to reduce the total amount of simulation that is done, or simply to simulate a less complex model. However, this increases the risk of producing a faulty circuit. Unfortunately, these methods are quite common in today´s competitive hardware design industry. The company that first releases a new and better design is the one most likely to survive. Hence, there are some serious doubts in the hardware design community that existing HDL tools are suitable for large, complex designs. However, ways exist to improve the situation. One approach we believe is promising is to use parallel simulation methodologies