• DocumentCode
    1241496
  • Title

    The drain threshold voltage VTd in submicrometer MOS transistors at 4.2 K

  • Author

    Edmundo, A. ; Gutierrez, D.

  • Author_Institution
    Integrated Circuit´s Design Group, Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico
  • Volume
    16
  • Issue
    3
  • fYear
    1995
  • fDate
    3/1/1995 12:00:00 AM
  • Firstpage
    85
  • Lastpage
    87
  • Abstract
    In this paper a set of experimental results of the so-called drain threshold voltage V/sub Td/, and its impact on the electrical performance of submicrometer MOS transistors, are presented. This effect is more pronounced when the device is operated in a cryogenic ambient. Therefore, by reducing the temperature down to 4.2 K, the V/sub Td/ mechanism, which is not visible at room temperature, is amplified and more easily related to the negative overlapping source-gate length (-/spl Delta/L). In this way it is found that the devices with a larger V/sub Td/ are the ones with a more negative /spl Delta/L, showing that the V/sub Td/ and the -/spl Delta/L are correlated and have the same physical origin. Moreover, it is suspected that the reverse short-channel effect (RSCE) might be also correlated to the V/sub Td/ effect.<>
  • Keywords
    MOSFET; cryogenic electronics; 4.2 K; MOS transistors; cryogenic ambient; drain threshold voltage; electrical performance; negative overlapping source-gate length; reverse short-channel effect; submicrometer MOSFET; submicron device; CMOS technology; Cryogenics; Extraterrestrial measurements; Linear approximation; MOS devices; MOSFETs; Packaging; Parasitic capacitance; Temperature; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.363232
  • Filename
    363232