Title :
Enhancement mode InP MISFET´s with sulfide passivation and photo-CVD grown P3N5 gate insulators
Author :
Jeong, Yoon-Ha ; Jo, Seong-Kue ; Lee, Bong-Hoon ; Sugano, Takuo
Author_Institution :
Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea
fDate :
3/1/1995 12:00:00 AM
Abstract :
High performance enhancement mode InP MISFET´s have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P/sub 3/N/sub 5/ film used as gate insulator. The MISFET´s thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10/sup 4/ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm/sup 2V/spl middot/s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6/spl times/10/sup 14cm/sup 2/ eV has been attained.<>
Keywords :
III-V semiconductors; MISFET; electron mobility; indium compounds; interface states; passivation; semiconductor-insulator boundaries; stability; 2 to 4 V; 2.7 mS/mm; InP-P/sub 3/N/sub 5/; MISFET; P/sub 3/N/sub 5/ gate insulators; capacitance-voltage characteristics; drain current stability; effective electron mobility; enhancement mode; extrinsic transconductance; high performance devices; interface trap states; photo-CVD grown gate insulators; sulfide passivation; Electron mobility; Hysteresis; Indium phosphide; Insulation; Interface states; Passivation; Stability; Temperature; Transconductance; Voltage;
Journal_Title :
Electron Device Letters, IEEE
