Current-Mode Phase-Locked Loops With CMOS Active Transformers

This paper introduces active transformer current- mode phase-locked loops (PLLs). The proposed PLLs replaces the RC loop filter of voltage-mode PLLs with an active transformer loop filter to take the advantage of their large inductance and small silicon area. A current-controlled LC oscillator with active inductors is employed to further reduce silicon area. The sensitivity of the cutoff frequency of active transformer loop filter to supply voltage fluctuation and process variation is analyzed. A 3-GHz PLL has been implemented in TSMC 0.18-mum 6-metal 1.8-V CMOS technology and analyzed using SpectreRF with BSIM3v3 device models and Verilog-AMS from cadence design systems. The lock time of the PLL is 60 ns. The power consumption and phase noise of the PLL are 16 m W and -100 dBc/Hz at 1-MHz frequency offset, respectively. The layout area of the PLL is 2800 mum².