Parallel constant-time connectivity algorithms on a reconfigurable network of processors

This short note presents constant-time algorithms for labeling the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N×N image in O(1) time using N² processors, which is optimal. Furthermore, the proposed techniques lead to an O(logN/loglogN)-time image labeling algorithm on a network of N² processors with a reconfigurable bus of width log N bits. It is shown that these techniques on be applied to labeling an undirected N-vertex graph represented by an adjacency matrix