Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six- input look-up tables.