Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI

Author

Van Ierssel, Marcus ; Yamaguchi, Hisakatsu ; Sheikholeslami, Ali ; Tamura, Hirotaka ; Walker, William W.

Author_Institution

Snowbush Microelectron., Toronto, ON

Volume

55

Issue

5

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1306

Lastpage

1315

Abstract

This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector´s front-end sampler, and intersymbol interference in the system´s channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.

Keywords

SPICE; decision circuits; intersymbol interference; noise; phase detectors; synchronisation; timing jitter; CDR jitter; Hspice simulation; Simulink; channel intersymbol interference; clock-and-data recovery systems; continuous-time jitter sources; event-driven modeling; finite decision circuit bandwidth; phase detector´s front-end sampler; power supply noise; sample based phase detectors; Bandwidth; Circuit noise; Circuit simulation; Clocks; Discrete event simulation; Intersymbol interference; Jitter; Phase detection; Phase noise; Power system modeling; Clock jitter; clock-and-data recovery (CDR) modeling; discrete-time simulation; event driven;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2008.916454

Filename

4539054