Digital Multiplier Power Estimates

Multiplication is an essential operation in digital signalprocessing algorithms. In such applications the organization of a multiplier typically ranges from parallel array to serial-parallel pipeline, with many intermediate possibilities. In this concise paper, the parallel array and serial-parallel pipeline organizations are compared on the basis of the power dissipation needed to achieve a specified multiplication rate. The first-order comparison is intended to serve as a preliminary aid in the design of custom integrated multiplier circuits. The comparison illuminates the differences in circuit technology appropriate for the two organizations. It also indicates that, insofar as custom integrated circuit design is concerned, design parameters other than power dissipation are likely to be the dominant considerations in choosing a multiplier organization.