• DocumentCode
    1243221
  • Title

    High performance dense ring generators

  • Author

    Mrugalski, Grzegorz ; Mukherjee, Nilanjan ; Rajski, Janusz ; Tyszer, Jerzy, Sr.

  • Author_Institution
    Mentor Graphics, Wikonville, OR, USA
  • Volume
    55
  • Issue
    1
  • fYear
    2006
  • Firstpage
    83
  • Lastpage
    87
  • Abstract
    This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.
  • Keywords
    built-in self test; design for testability; parallel processing; shift registers; system-on-chip; built-in self-test; design for testability; high performance dense ring generator; linear feedback shift registers; on-chip pseudorandom test pattern generator; phase shifter; test data decompressor; test response compactor; Design for testability; Parallel processing; Self-testing; Shift registers; Index Terms- Built-in self-test; design for testability; linear feedback shift registers; phase shifters; ring generators.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2006.11
  • Filename
    1545753
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1243221