Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications

A QAM processor for applications in QAM demodulators with baud rates of up to 60 Mbaud and modulation schemes of up to 1024 QAM has been implemented on a single chip. The chip performs 11-tap complex-valued adaptive time-domain equalization and the complete digital base-band signal processing of high-capacity QAM demodulators. This includes frequency-domain slope equalization and the digital parts of the timing and carrier recovery as well as the gain and offset control for the A-to-D converters. The equalizer can be operated in baud spaced and half-baud spaced mode and can also be applied for cross-polarization interference cancellation. The computational power of the QAM processor exceeds 6 giga-multiply-accumulate operations per second. Fabricated in an 1.0-μm CMOS technology on a silicon area of 185 mm² this 800 K-transistor chip demonstrates the potential of such low-cost technologies. The maximum clock frequency under worst-case conditions is 60 MHz. The corresponding power dissipation is 4.2 W