Title :
A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer
Author :
Ohkubo, Norio ; Suzuki, Makoto ; Shinbo, Toshinobu ; Yamanaka, Toshiaki ; Shimizu, Akihiro ; Sasaki, Kazuhiko ; Nakagome, Yoshinobu
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
3/1/1995 12:00:00 AM
Abstract :
A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply
Keywords :
CMOS logic circuits; adders; floating point arithmetic; multiplying circuits; 0.25 micron; 2.5 V; 4-2 compressor; 4.4 ns; 54 bit; 54×54-bit configuration; CMOS technology; carry lookahead adder; multiplier; pass-transistor multiplexer; Adders; CMOS logic circuits; CMOS technology; Carbon capture and storage; Delay effects; Digital signal processing; Graphics; Multiplexing; Power supplies; Reduced instruction set computing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
