DocumentCode
1243711
Title
Substrate-aware mixed-signal macrocell placement in WRIGHT
Author
Mitra, Sujoy ; Rutenbar, Rob A. ; Carley, L.R. ; Allstot, David J.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Volume
30
Issue
3
fYear
1995
fDate
3/1/1995 12:00:00 AM
Firstpage
269
Lastpage
278
Abstract
We describe a set of placement algorithms for handling substrate coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed-signal placement optimization
Keywords
cellular arrays; circuit layout CAD; integrated circuit layout; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; simulated annealing; substrates; WRIGHT; automatic placement; automatic placement framework; digital switching transients; digital/analog interactions; first-cut chip-level placement; isolation techniques; layout CAD; mixed-signal IC; mixed-signal macrocell placement; mixed-signal placement optimization; noisy digital macrocells; placement algorithms; sensitive analog regions; substrate coupled switching noise; substrate model; substrate-aware algorithms; substrate-noise evaluation mechanism; Analog integrated circuits; Circuit noise; Circuit simulation; Coupling circuits; Digital integrated circuits; Integrated circuit noise; Macrocell networks; Predictive models; Semiconductor device noise; Substrates;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.364441
Filename
364441
Link To Document