Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories

Author

Domer, Steven M. ; Foertsch, Samuel A. ; Raskin, Glenn D.

Author_Institution

Semicond. Products Sector, Motorola Inc., Chandler, AZ, USA

Volume

30

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

286

Lastpage

294

Abstract

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP´s and QFP´s to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; VLSI; bipolar integrated circuits; economics; integrated circuit layout; integrated circuit manufacture; integrated circuit modelling; integrated circuit yield; integrated memory circuits; BiCMOS process; CMOS process; VLSI designs; VLSI floorplanning; bipolar process; circuit redundancy; layout sensitivity; manufacturing cost; manufacturing costs prediction; memories; mixed circuitry; yield model; yield prediction; BiCMOS integrated circuits; CMOS process; Circuit testing; Costs; Electronics packaging; Flip chip; Predictive models; Semiconductor device modeling; Very large scale integration; Virtual manufacturing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.364443

Filename

364443