ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (underVSS). The LVTp-n-p devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-μm CMOS process have proven that the ESD level of the proposed LVTp-n-p is higher than that of the traditional p-n-p device. Furthermore, layout on LVTp-n-p device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35- and 0.25-μm CMOS processes have proven that the ESD levels of the LVTp-n-p drawn in the multifinger layout style are higher than that drawn in the single-finger layout style. Moreover, one of the LVT p-n-p devices drawn with the multifinger layout style has been used to successfully protect the input stage of an asymmetric digital subscriber line (ADSL) IC in a 0.25-μm salicided CMOS process.