DocumentCode :
1244460
Title :
Optimum positioning of interleaved repeaters in bidirectional buses
Author :
Ghoneima, Maged ; Ismail, Yehea
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Volume :
24
Issue :
3
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
461
Lastpage :
469
Abstract :
It is shown in this paper that the optimum position of interleaved repeaters for minimum delay and noise is not the midpoint as commonly practiced. A closed-form solution for the optimum position has been derived in this paper and verified by simulation. Bidirectional buses with the optimum interleaved repeater position are compared to commonly used bidirectional buses and shown to provide an improvement greater than 50% in the propagation delay and bit-rate per unit area. The area of the induced noise pulse on victim lines is shown to be zero indicating that the aggressor lines are virtually static with the optimum repeater position. The presented optimum repeater positioning also provides lower noise pulse amplitude as well as lower sensitivity of propagation delay and noise pulse peak to segment length variation, compared to commonly used midway repeater positioning.
Keywords :
capacitance; circuit optimisation; delays; integrated circuit design; integrated circuit noise; repeaters; system buses; bidirectional buses; bit-rate; closed-form solution; coupling capacitance; induced noise pulse; midway repeater positioning; minimum delay; minimum noise; noise pulse amplitude; noise pulse peak; on-chip buses; optimum interleaved repeater position; propagation delay; repeater insertion; segment length variation; signal integrity; Capacitance; Coupling circuits; Crosstalk; Integrated circuit interconnections; Integrated circuit noise; Noise level; Propagation delay; Repeaters; Semiconductor device noise; Switches; Bidirectional buses; coupling capacitance; delay; interleaved repeaters; noise; on-chip buses; repeater insertion; signal integrity;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.842801
Filename :
1397805
Link To Document :
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