Parallelism in analog and digital PRML magnetic disk read channel equalizers

Analog pre-equalization can play an important role in the performance and monolithic implementation of high speed PRML read channels employing detection in the digital domain by reducing the number of quantization levels required in the analog-to-digital converter. The use of the 3-tap raised cosine equalizer as an analog pre-equalizer in a read channel employing digital adaptive equalization is examined. Following this, a parallel filter architecture suitable for implementation of high speed finite-impulse response filters (including the cosine equalizer) in both the analog and digital domain is described. This parallel filter architecture has been used in the analog domain in both a decimation filter and cosine equalizer in a prototype analog-to-digital interface and in the digital domain in a prototype digital adaptive equalizer/Viterbi sequence detector. Both circuits were fabricated in conservative 1.2 /spl mu/m CMOS technologies and operate with output sampling rates of 100 MHz.<>