A high speed, low power PRML read channel device

Author

Sonntag, J. ; Agazzi, O. ; Aziz, P. ; Burger, H. ; Comino, V. ; Heimann, M. ; Karanink, T. ; Khoury, J. ; Madine, S. ; Nagaraj, K. ; Offord, G. ; Peruzzi, R. ; Plany, J. ; Rao, N. ; Sayiner, N. ; Setty, P. ; Threadgill, K.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

Volume

31

Issue

2

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

1186

Lastpage

1195

Abstract

A complete read channel device using PR-IV signalling and maximum likelihood detection is described. Descriptions, simulated performance and measured results of the digital adaptive feedback loops (AGC, FIR tap weights, DFE tap weights, frequency and phase) in the read channel are presented. Analog FIR filter and hash A/D converter performance is presented. The weighted averaging servo demodulation technique used in the device is described and compared to integration. This monolithic CMOS device consumes less than 0.75 W when reading at 85 Mbps, and occupies a step-and-repeat area of 24.6 mm/sup 2/.<>

Keywords

CMOS integrated circuits; FIR filters; analogue-digital conversion; maximum likelihood detection; partial response channels; 0.75 W; 85 Mbit/s; AGC; DFE tap weights; FIR tap weights; PR-IV signalling; analog FIR filter; digital adaptive feedback loops; frequency; hash A/D converter; high speed low power PRML read channel device; integration; maximum likelihood detection; monolithic CMOS device; phase; simulation; step-and-repeat area; weighted averaging servo demodulation; Circuit testing; Decision feedback equalizers; Demodulation; Digital filters; Feedback loop; Finite impulse response filter; Frequency measurement; Maximum likelihood detection; Phase measurement; Servomechanisms;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/20.364805

Filename

364805