Design, performance, and extensions of the RAM-DFE architecture

Author

Bednarz, P.S. ; Lin, S.C. ; Modlin, C.S. ; Cioffi, J.M.

Author_Institution

Inf. Syst. Lab., Stanford Univ., CA, USA

Volume

31

Issue

2

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

1196

Lastpage

1201

Abstract

The design and performance of an adaptive RAM-Decision feedback equalizer integrated circuit (RAM-DFE IC) for magnetic recording channels is presented. The 0.8 /spl mu/m BICMOS digital chip has been integrated with discrete analog components in a 54 Mbps read channel. Description of the IC implementation details techniques to reduce latency and outlines tradeoffs between performance and complexity. In an effort to achieve higher throughput, alternative decision feedback loop architectures based on look-ahead computation are evaluated. A hybrid RAM/linear architecture is found to approach 150 Mbps throughput with implementational advantages over both RAM and linear feedback filters.<>

Keywords

BiCMOS digital integrated circuits; adaptive equalisers; decision feedback equalisers; magnetic recording; random-access storage; 0.8 micron; 150 Mbit/s; 54 Mbit/s; BICMOS digital chip; RAM-DFE IC; adaptive RAM-Decision feedback equalizer integrated circuit; decision feedback loop architectures; design; discrete analog components; hybrid RAM/linear architecture; latency; linear feedback filters; look-ahead computation; magnetic recording channels; BiCMOS integrated circuits; Computer architecture; Decision feedback equalizers; Delay; Feedback loop; Finite impulse response filter; Magnetic recording; Magnetic separation; Nonlinear filters; Throughput;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/20.364806

Filename

364806