Detailed investigation of geometrical factor for pseudo-MOS transistor technique

Author

Komiya, Kenji ; Bresson, Nicolas ; Sato, Shingo ; Cristoloveanu, Sorin ; Omura, Yasuhisa

Author_Institution

High-Technol. Res. Center, Kansai Univ., Osaka, Japan

Volume

52

Issue

3

fYear

2005

fDate

3/1/2005 12:00:00 AM

Firstpage

406

Lastpage

412

Abstract

The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility.

Keywords

MOSFET; carrier mobility; probes; silicon-on-insulator; Ψ-MOSFET; SOI; accurate characterization; as-fabricated silicon-on-insulator wafers; carrier mobility; drain current; geometrical factor; probe-pressure effects; probe-to-edge distance; pseudo-MOS transistor technique; sample size effects; silicon island size; Current measurement; Electrodes; Helium; MOSFETs; Pressure effects; Probes; Silicon on insulator technology; Substrates; Threshold voltage; Transconductance; Carrier mobility; geometrical factor; probe pressure; pseudo-MOS (; silicon-on-insulator (SOI);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.843970

Filename

1397991