Improving the activation of the P+ region of low-temperature polycrystalline Si TFTs by using solid-phase Crystallization

We have developed a low-temperature fabrication process for making thin-film transistors (TFTs) with highly activated source and drain regions by utilizing pre-amorphization by Ge-ion implantation followed by solid-phase crystallization. The sheet resistances of the p⁺ polysilicon layers formed by B-ion implantation with and without Ge-ion implantation were, respectively, 200 and 1500 Ω/sq. We confirmed reducing the sheet resistance of p⁺ polysilicon increases the on-current of TFTs on glass substrates. This process is promising for making high-performance CMOS peripheral circuits for liquid crystal display panels.