Title :
Pixel processing in a memory controller
Author :
Donovan, Walt ; Sabella, Paolo ; Kabir, Ihtisham ; Hsieh, Michael M.
Author_Institution :
Synema Corp., Palo Alto, CA, USA
fDate :
1/1/1995 12:00:00 AM
Abstract :
The SX-a programmable pixel processor implemented in a workstation memory controller chip-aims to perform as well as low-end 2D and 3D graphics processors and to surpass low-end imaging accelerators. The following features help accomplish this goal: large internal register set; vectorized RISC-like instruction set; fast access to both main and video memory; fast pixel operations; free operations; unpolluted cache; and single-chip solution. We describe the workstation configuration we used for our tests and the SX processor architecture, followed by the SX instruction set and sample algorithms. Then we present SX performance results for a wide range of operations
Keywords :
cache storage; computer graphic equipment; digital signal processing chips; image processing equipment; memory architecture; performance evaluation; reduced instruction set computing; workstations; SX performance; SX processor architecture; SX programmable pixel processor; fast access; fast pixel operations; free operations; large internal register set; main memory; sample algorithms; single-chip solution; tests; unpolluted cache; vectorized RISC-like instruction set; video memory; workstation configuration; workstation memory controller chip; Clocks; Costs; Displays; Graphics; Image processing; Pixel; Random access memory; Registers; Rendering (computer graphics); Workstations;
Journal_Title :
Computer Graphics and Applications, IEEE
