Title :
Efficient diminished-1 modulo 2n + 1 multipliers
Author :
Efstathiou, Costas ; Vergos, Haridimos T. ; Dimitrakopoulos, Giorgos ; Nikolos, Dimitris
Author_Institution :
Dept. of Informatics, TEI of Athens, Greece
fDate :
4/1/2005 12:00:00 AM
Abstract :
In this work, we propose a new algorithm for designing diminished-1 modulo 2n+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.
Keywords :
VLSI; cryptography; multiplying circuits; residue number systems; tree data structures; VLSI design; computer arithmetic; fermat number transform; modulo 2n+1multiplier; residue number system; tree architecture; Algorithm design and analysis; Application software; Computer architecture; Convolution; Cryptography; Digital arithmetic; Digital signal processors; Roundoff errors; Signal processing algorithms; Very large scale integration; Fermat number transform; Index Terms- Modulo 2^n+1 multipliers; VLSI design.; computer arithmetic; residue number system;
Journal_Title :
Computers, IEEE Transactions on
