Wave-domino logic: theory and applications

Wave-pipelining has been investigated extensively as a design method to increase clock frequencies of digital systems. Data are clocked into a combinational circuit with a clock period smaller than the latency of the combinational block. To achieve the minimal period, collisions among waves must be avoided by balancing the delay paths from inputs to all intermediate nodes and outputs. Process variation and environmental influences have also to be taken into account in the design. While previous research has explored wave-pipelining of ECL and static CMOS circuits, we concentrate on CMOS domino circuits because of their compact layouts and shorter delay time. A timing model and constraints are given for deriving the minimal period. Special partitioning and delay assignment problems are discussed. Process variation is modeled by characterizing the current drive capabilities of N and P devices. A test chip has been designed, fabricated, and tested which uses a novel form of domino-logic to implement a wave-domino multiplier, sum of product trees, and a parity checker