Title :
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement
Author :
Shu-Meng Yang ; Meng-Fan Chang ; Chi-Chuang Chiang ; Ming-Pin Chen ; Yamauchi, Hiroyuki
Author_Institution :
Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Density-prioritized memories such as NAND-ROM require a longer single-ended bitline (BL) sensing scheme to maintain high cell array efficiency and therefore suffer from a reduced BL sensing margin at ultra-low supply voltages (VDD) for read-0. This is the result of 1) reduced BL discharge driving current due to limited cell size and driving voltage; and 2) a larger BL false drop noise for read-1. This study proposes a data-aware sensing reference (DASR) scheme, capable of maintaining sensing margins for both read-0 and read-1 under given timing constraints. The key mechanism involved in maintaining the sensing margin is the adaptive changing of the reference voltage (VREF), such that the sensing headroom or potential range (VBL-VREF) for read-1 and read-0 overlap, as in differential BL sensing. Two 256 Kb DASR NAND-ROM macros, with and without code-inversion schemes, were fabricated using a 90 nm bulk CMOS logic process. The 256 Kb DASR NAND-ROM macros are functional down to 0.25 V. DASR also increases the access speed by 66.7% at 0.31 V VDD, compared with the conventional approach without the proposed DASR scheme.
Keywords :
CMOS logic circuits; CMOS memory circuits; discharges (electric); embedded systems; logic gates; macros; power supplies to apparatus; read-only storage; BL discharge driving current; BL false drop noise; BL sensing margin; DASR NAND-ROM macros; VDD; VDDmin; bulk CMOS logic; code-inversion schemes; data-aware sensing reference scheme; density-prioritized memories; driving voltage; high cell array efficiency; limited cell size; low-voltage embedded NAND-ROM macros; potential range; power improvement; read-0; read-1; sensing headroom; single-ended BL sensing scheme; single-ended bitline sensing scheme; size 90 nm; speed improvement; storage capacity 256 Kbit; timing constraints; ultra-low supply voltages; voltage 0.31 V; Arrays; Noise; Read only memory; Sensors; Stacking; Timing; Transistors; Low voltage; NAND-ROM; ROM; VDDmin; reference voltage; sense amplifier;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2012.2229068