A 22-kHz multibit switched-capacitor sigma-delta D/A converter with 92 dB dynamic range

Author

Ju, Peicheng ; Suyama, Ken ; Ferguson, Paul F., Jr. ; Lee, Wai

Author_Institution

Lab. for Microelectron. Circuits Res., Columbia Univ., New York, NY, USA

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1316

Lastpage

1325

Abstract

A time- and capacitor-multiplexing technique for use in a highly linear switched-capacitor multibit DAC in sigma-delta data converters is presented. The technique uses subintervals in the sample clock to deliver multiple charge packets to holding capacitors. It avoids distortion effects caused by mismatched capacitors and finite opamp gain. A five-level switched-capacitor DAC using the proposed technique was designed as part of an audio-band multibit sigma-delta D/A converter that achieved a dynamic range of 92 dB and a THD of -93 dB with a low oversampling ratio of 32. No trimming, calibration, or dynamic matching scheme was required. The five-level SC DAC has been fabricated in a 2-μm CMOS process, and testing confirmed the anticipated theoretical results

Keywords

CMOS integrated circuits; digital-analogue conversion; harmonic distortion; sigma-delta modulation; switched capacitor networks; time division multiplexing; 2 micron; 22 kHz; CMOS process; THD; capacitor-multiplexing technique; dynamic range; holding capacitors; multibit switched-capacitor sigma-delta D/A converter; multiple charge packets; oversampling ratio; time-multiplexing technique; Analog-digital conversion; Calibration; Capacitors; Circuits; Delta-sigma modulation; Dynamic range; Linearity; Quantization; Semiconductor device noise; Switching converters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482157

Filename

482157