A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

Author

Craninckx, Jan ; Steyaert, Michel S J

Author_Institution

Dept. Elektrotech., Katholieke Univ., Leuven, Belgium

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1474

Lastpage

1482

Abstract

The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-μm CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; inductors; lead bonding; phase locked loops; phase noise; prescalers; voltage-controlled oscillators; 0.7 micron; 1.8 GHz; 28 mW; 3 V; 8 mA; CMOS; ECL-alike high-frequency D-flipflop; LC-tuned oscillators; bondwire inductors; fixed division ratio; frequency-synthesizing PLL; low-phase-noise voltage-controlled oscillator; on-chip bondwires; power consumption; prescaler; Active inductors; Active noise reduction; Bonding; CMOS technology; Circuit noise; Frequency synthesizers; Gyrators; Phase noise; Telephony; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482195

Filename

482195