Digital FIR filters for high speed PRML disk read channels

Author

Pearson, Dale J. ; Reynolds, Scott K. ; Megdanis, Andrew C. ; Gowda, Sudhir ; Wrenner, Kevin R. ; Immediato, Michael ; Galbraith, Richard L. ; Shin, Hyun J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1517

Lastpage

1523

Abstract

This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology

Keywords

BiCMOS digital integrated circuits; FIR filters; digital arithmetic; digital filters; digital magnetic recording; digital signal processing chips; equalisers; magnetic disc storage; maximum likelihood detection; partial response channels; 0.5 micron; 20 Mbyte/s; 6 bit; BiCMOS DSP chip; PRML disk read channels; channel equalization; custom circuit design; digital FIR filters; distributed-arithmetic architecture; high sampling rates; high speed read channels; Adders; Arithmetic; Circuit synthesis; Design optimization; Digital filters; Finite impulse response filter; Latches; Partial response signaling; Sampling methods; Shift registers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482200

Filename

482200