114 MFLOPS logarithmic number system arithmetic unit for DSP applications

Author

Lewis, David M.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1547

Lastpage

1553

Abstract

An arithmetic core for DSP applications, comprising two multiplier/dividers and an adder/subtractor, using logarithmic number system (LNS) arithmetic, is described. For most operands, precision better than the worst-case precision of IEEE 754 is obtained. Three operations per cycle are performed using 69k transistors integrated in a 16 mm² core in 1.2 μm CMOS, offering better performance than the best previous result in only 43% of the area. The use of a new interleaved memory ROM structure and a second-order function interpolator are the key techniques that result in reduced area. This modest area allows several core units to be integrated on a chip for high performance DSP applications

Keywords

CMOS logic circuits; arithmetic; digital arithmetic; digital signal processing chips; interpolation; 1.2 micron; 114 MFLOPS; CMOS chip; DSP applications; adder/subtractor; arithmetic unit; interleaved memory ROM structure; logarithmic number system; multiplier/dividers; second-order function interpolator; Arithmetic; Clocks; Digital filters; Digital signal processing; Digital signal processing chips; Dynamic range; Microwave integrated circuits; Pervasive computing; Read only memory; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482205

Filename

482205