A 10 Mb frame buffer memory with Z-compare and A-blend units

Author

Inoue, Kazunari ; Nakamura, Hisashi ; Kawai, Hiroyuki

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1563

Lastpage

1568

Abstract

A 3-D frame buffer memory that integrates Z-compare and A-blend units onto a 10 Mb DRAM chip is presented. High I/O bandwidth and a new pixel ALU implementation greatly Improve rendering performance. The 3-D-RAM converts the fundamental rendering operation from read-modify-write into mostly-write. A triple-ported SRAM cache operating at a frequency of 100 MHz and an internal 256-b wide bus accelerate rendering operations to 400 Mpixel/s, ten times faster than conventional DRAM or VRAM. A VIDEO port is provided for CRT refresh with less than 2% area penalty by virtue of a rectangular shaped page. A quad-polysilicon, double metal, 0.5 μm CMOS process is employed

Keywords

CMOS memory circuits; DRAM chips; SRAM chips; buffer storage; computer graphic equipment; rendering (computer graphics); 0.5 micron; 10 Mbit; 100 MHz; 3D RAM; 3D buffer memory; 3D graphics applications; A-blend unit; CRT refresh; DRAM chip; Si; Z-compare unit; frame buffer memory; pixel ALU implementation; quad-polysilicon double metal CMOS process; rectangular shaped page; rendering operation; triple-ported SRAM cache; video port; Acceleration; Bandwidth; CMOS process; Cathode ray tubes; Costs; Frequency; Graphics; Random access memory; Rendering (computer graphics); Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482207

Filename

482207