Title :
A design of Reed-Solomon decoder with systolic-array structure
Author :
Iwamura, Keiichi ; Dohi, Yasunori ; Imai, Hideki
Author_Institution :
Dept. of Imaging Res., Canon Inc., Tokyo, Japan
fDate :
1/1/1995 12:00:00 AM
Abstract :
This brief contribution proposes a new class of systolic-arrays to perform Binary Reed-Solomon (RS) decoding procedures including erasure correction. Such RS decoder is suitable for VLSI implementation since the arrays consist of simple processing elements of the same type
Keywords :
Reed-Solomon codes; codecs; decoding; error correction codes; systolic arrays; Reed-Solomon decoder; VLSI implementation; erasure correction; error correction; high-speed processing; systolic-array; Computer architecture; Computer errors; Decoding; Error correction; Error correction codes; Optical computing; Pipelines; Polynomials; Reed-Solomon codes; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
